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if diversity receiver AD6649 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features snr = 73.0 dbfs in a 95 mhz bandwidth at 185 mhz a in and 245.76 msps sfdr = 85 dbc at 185 mhz a in and 250 msps noise density = ?151.2 dbfs/hz input at 185 mhz, ?1 dbfs a in and 250 msps total power consumption: 1 w with fixed-frequency nco, 95 mhz fir filter 1.8 v supply voltages lvds (ansi-644 levels) outputs integer 1-to-8 input clock divider (625 mhz maximum input) integrated dual-channel adc sample rates of up to 250 msps if sampling frequencies to 400 mhz internal adc voltage reference flexible input range 1.4 v p-p to 2.1 v p-p (1.75 v p-p nominal) adc clock duty cycle stabilizer 95 db channel isolation/crosstalk integrated wideband digital processor 32-bit complex numerically controlled oscillator (nco) fir filter with 2 modes real output from an f s /4 output nco amplitude detect bits for efficient agc implementation energy saving power-down modes decimated, interleaved real lvds data outputs applications communications diversity radio systems multimode digital receivers (3g) td-scdma, wimax, wcdma, cdma2000, gsm, edge, lte general-purpose software radios broadband data applications general description the AD6649 is a mixed-signal intermediate frequency (if) receiver consisting of dual 14-bit, 250 msps adcs and a wideband digital downconverter (ddc). the AD6649 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired. the dual adc cores feature a multistage, differential pipelined architecture with integrated output error correction logic. each adc features wide bandwidth inputs supporting a variety of user-selectable input ranges. an integrated voltage reference eases design considerations. a duty cycle stabilizer is provided to compensate for variations in the adc clock duty cycle, allowing the converters to maintain excellent performance. functional block diagram dc correction adc threshold detect avdd fd a drvdd AD6649 v in+ a v in? a fdb dc correction reference adc i q q i v in?b v in+b d13+/d13? d0+/d0? clk+ clk? dco+ dco? divide 1 to 8 duty cycle stabilizer agnd sdio sclk csb spi programming data threshold detect selectable fir filter selectable fir filter digital interleaving f s /4 nco or+ or? oeb pdwn dco generation sync multichip sync 09635-001 ddr lvds output buffer selectable fir filter selectable fir filter 32-bit tuning nco figure 1.
AD6649 rev. 0 | page 2 of 40 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? product highlights ........................................................................... 3 ? specifications..................................................................................... 4 ? adc dc specifications................................................................. 4 ? adc ac specifications ................................................................. 5 ? digital specifications ..................................................................... 6 ? switching specifications ................................................................ 8 ? timing specifications .................................................................. 9 ? absolute maximum ratings.......................................................... 10 ? thermal characteristics ............................................................ 10 ? esd caution................................................................................ 10 ? pin configuration and function descriptions........................... 11 ? typical performance characteristics ........................................... 13 ? equivalent circuits ......................................................................... 16 ? theory of operation ...................................................................... 17 ? adc architecture ...................................................................... 17 ? analog input considerations.................................................... 17 ? voltage reference ....................................................................... 19 ? clock input considerations ...................................................... 19 ? power dissipation and standby mode..................................... 20 ? digital outputs ........................................................................... 21 ? digital processing ........................................................................... 22 ? numerically controlled oscillator (nco) ............................. 22 ? nco and fir filter modes....................................................... 22 ? f s /4 fixed-frequency nco ....................................................... 22 ? numerically controlled oscillator (nco) ................................. 23 ? frequency translation ............................................................... 23 ? nco synchronization ............................................................... 23 ? nco amplitude and phase dither.......................................... 23 ? fir filters ........................................................................................ 24 ? fir synchronization .................................................................. 24 ? filter performance...................................................................... 24 ? output nco ............................................................................... 25 ? adc overrange and gain control.............................................. 26 ? adc overrange (or)................................................................ 26 ? gain switching............................................................................ 26 ? dc correction ................................................................................ 27 ? channel/chip synchronization.................................................... 28 ? serial port interface (spi).............................................................. 29 ? configuration using the spi..................................................... 29 ? hardware interface..................................................................... 29 ? spi accessible features.............................................................. 30 ? memory map .................................................................................. 31 ? reading the memory map register table............................... 31 ? memory map register table..................................................... 32 ? memory map register description ......................................... 36 ? applications information .............................................................. 39 ? design guidelines ...................................................................... 39 ? outline dimensions ....................................................................... 40 ? ordering guide .......................................................................... 40 ? revision history 4/11revision 0: initial version
AD6649 rev. 0 | page 3 of 40 adc data outputs are internally connected directly to the digital downconverter (ddc) of the receiver. the digital receiver has two channels and provides processing flexibility. each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (nco)), an optional sample rate converter, a fixed fir filter, and an f s /4 fixed-frequency nco. in addition to the receiver ddc, the AD6649 has several functions that simplify the automatic gain control (agc) function in the system receiver. the programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the adc. if the input signal level exceeds the programmable threshold, the fast detect indicator goes high. because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the adc input. after digital processing, data is routed directly to the 14-bit output port. these outputs operate at ansi or reduced swing lvds signal levels. the AD6649 receiver digitizes a wide spectrum of if frequencies. each receiver is designed for simultaneous reception of the main channel and the diversity channel. this if sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. in diversity applications, the output data format is real due to the final nco, which shifts the output center frequency to f s /4. flexible power-down options allow significant power savings, when desired. programming for setup and control is accomplished using a 3-pin spi-compatible serial interface. the AD6649 is available in a 64-lead lfcsp and is specified over the industrial temperature range of ?40c to +85c. this product is protected by a u.s. patent. product highlights 1. integrated dual, 14-bit, 250 msps adcs. 2. integrated wideband filter and 32-bit complex nco. 3. fast overrange and threshold detect. 4. proprietary differential input maintains excellent snr performance for input frequencies of up to 400 mhz. 5. sync input allows synchronization of multiple devices. 6. 3-pin, 1.8 v spi port for register programming and register readback.
AD6649 rev. 0 | page 4 of 40 specifications adc dc specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1 1.75 v p-p full-scale input range, duty cycle stabilizer (dcs) enabled, nco enabled, fir filter enabled, unless otherwise noted. table 1. parameter temperature min typ max unit resolution full 14 bits accuracy no missing codes full guaranteed offset error full 10 mv gain error full ?5.5 +2.5 %fsr matching characteristic offset error full 13 mv gain error full 2.5 %fsr temperature drift offset error full 15 ppm/c gain error full 50 ppm/c input referred noise vref = 1.0 v 25c 1.32 lsb rms analog input input span full 1.75 v p-p input capacitance 2 full 2.5 pf input resistance 3 full 20 k input common-mode voltage full 0.9 v power supplies supply voltage avdd full 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 v supply current i avdd 4 full 271 275 ma i drvdd 4 (fixed-frequency nco, 95 mhz fir filter) full 283 300 ma i drvdd 4 (tunable-frequency nco, 100 mhz fir filter) full 375 ma power consumption sine wave input (fixed-frequency nco, 95 mhz fir filter) full 997 1035 mw sine wave input (tunable-frequency nco, 100 mhz fir filter) full 1163 mw standby power 5 full 104 mw power-down power full 10 mw 1 a ?1.0 dbfs input level at the analog inputs corresponds to an output level of ?2.5 dbfs when using the fixed-frequency nco an d 95 mhz fir filter. when using the tunable-frequency nco and 100 mhz fir filter, the output level is ?1 .3 dbfs. these respective outp ut level reductions are due t o fir filter losses. see the section for more details. fir filters 2 input capacitance refers to the effective capacitance between one differential input pin and agnd. 3 input resistance refers to the effective resistance between one differential input pin and its complement. 4 measured with a 185 mhz, full-scale sine wave input on both channels and an nco frequency of 62.5 mhz (f s /4). 5 standby power is measured with a dc input an d the clk pin inactive (set to avdd or agnd).
AD6649 rev. 0 | page 5 of 40 adc ac specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1 1.75 v p-p full-scale input range, dcs enabled, nco enabled, fir filter enabled, unless otherwise noted. table 2. parameter 2 temperature min typ max unit signal-to-noise ratio (snr) 3 f in = 30 mhz 25c 74.5 dbfs f in = 90 mhz 25c 74.2 dbfs f in = 140 mhz 25c 73.9 dbfs f in = 185 mhz 25c 73.4 dbfs full 70.9 dbfs f in = 220 mhz 25c 72.9 dbfs signal-to-noise and distortion (sinad) f in = 30 mhz 25c 73.4 dbfs f in = 90 mhz 25c 73.0 dbfs f in = 140 mhz 25c 72.3 dbfs f in = 185 mhz 25c 71.7 dbfs full 68.7 dbfs f in = 220 mhz 25c 71.0 dbfs worst second or third harmonic f in = 30 mhz 25c ?92 dbc f in = 90 mhz 25c ?88 dbc f in = 140 mhz 25c ?85 dbc f in = 185 mhz 25c ?85 dbc full ?80 dbc f in = 220 mhz 25c ?89 dbc spurious-free dynamic range (sfdr) f in = 30 mhz 25c 92 dbc f in = 90 mhz 25c 88 dbc f in = 140 mhz 25c 85 dbc f in = 185 mhz 25c 85 dbc full 80 f in = 220 mhz 25c 84 dbc worst other harmonic or spur f in = 30 mhz 25c ?95 dbc f in = 90 mhz 25c ?94 dbc f in = 140 mhz 25c ?93 dbc f in = 185 mhz 25c ?93 dbc full ?80 dbc f in = 220 mhz 25c ?84 dbc two-tone sfdr f in = 184.12 mhz, 187.12 mhz (?7 dbfs) 25c 88 dbc crosstalk 4 full 95 db analog input bandwidth 25c 1000 mhz 1 a ?1.0 dbfs input level at the analog inputs corresponds to an output level of ?2.5 dbfs when using the fixed-frequency nco an d 95 mhz fir filter. when using the tunable-frequency nco and 100 mhz fir filter, the output level is ?1 .3 dbfs. these respective outp ut level reductions are due t o fir filter losses. see the section for more details. fir filters 2 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions. 3 snr specifications are for filtered 95 mhz bandwidth. 4 crosstalk is measured at 100 mhz with ?1 dbfs on on e channel and with no input on the alternate channel.
AD6649 rev. 0 | page 6 of 40 digital specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1 1.0 v internal reference, dcs enabled, unless otherwise noted. table 3. parameter temperature min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl internal common-mode bias full 0.9 v differential input voltage full 0.3 3.6 v p-p input voltage range full agnd avdd v input common-mode range full 0.9 1.4 v high level input current full +10 +22 a low level input current full ?22 ?10 a input capacitance full 4 pf input resistance full 8 10 12 k sync input logic compliance cmos/lvds internal bias full 0.9 v input voltage range full agnd avdd v high level input voltage full 1.2 avdd v low level input voltage full agnd 0.6 v high level input current full ?5 +5 a low level input current full ?5 +5 a input capacitance full 1 pf input resistance full 12 16 20 k logic input (csb) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ?5 +5 a low level input current full ?80 ?45 a input resistance full 26 k input capacitance full 2 pf logic input (sclk) 3 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 70 a low level input current full ?5 +5 a input resistance full 26 k input capacitance full 2 pf logic input/output (sdio) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 70 a low level input current full ?5 +5 a input resistance full 26 k input capacitance full 5 pf logic inputs (oeb, pdwn) 3 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 70 a low level input current full ?5 +5 a
AD6649 rev. 0 | page 7 of 40 parameter temperature min typ max unit input resistance full 26 k input capacitance full 5 pf digital outputs fda and fdb high level output voltage i oh = 50 a full 1.79 v i oh = 0.5 ma full 1.75 v low level output voltage i ol = 1.6 ma full 0.2 v i ol = 50 a full 0.05 v lvds data and or outputs differential output voltage (v od ), ansi mode full 250 350 450 mv output offset voltage (v os ), ansi mode full 1.15 1.25 1.35 v differential output voltage (v od ), reduced swing mode full 150 200 280 mv output offset voltage (v os ), reduced swing mode full 1.15 1.25 1.35 v 1 a ?1.0 dbfs input level at the analog inputs corresponds to an output level of ?2.5 dbfs when using the fixed-frequency nco an d 95 mhz fir filter. when using the tunable-frequency nco and 100 mhz fir filter, the output level is ?1 .3 dbfs. these respective outp ut level reductions are due t o fir filter losses. see the section for more details. fir filters 2 pull-up. 3 pull-down.
AD6649 rev. 0 | page 8 of 40 switching specifications table 4. parameter temperature min typ max unit clock input parameters input clock rate full 625 mhz conversion rate 1 full 40 250 msps clk perioddivide-by-1 mode (t clk ) full 4.0 ns clk pulse width high (t ch ) divide-by-1 mode, dcs enabled full 1.8 2.0 2.2 ns divide-by-1 mode, dcs disabled full 1.9 2.0 2.1 ns divide-by-3 through divide-by-8 modes, dcs enabled full 0.8 ns data output parameters (data, or) data propagation delay (t pd ) full 4.8 ns dco propagation delay (t dco ) full 5.5 ns dco-to-data skew (t skew ) full 0.1 0.7 1.3 ns pipeline delayfixed-frequency nco, 95 mhz fir filter (latency) full 23 cycles pipeline delaytunable-frequency nco, 100 mhz fir filter (latency) full 43 cycles aperture delay (t a ) full 1.0 ns aperture uncertainty (jitter, t j ) full 0.1 ps rms wake-up time (from standby) full 10 s wake-up time (from power-down) full 250 s out-of-range recovery time full 3 cycles 1 conversion rate is the clock rate after the divider.
AD6649 rev. 0 | page 9 of 40 timing specifications table 5. parameter conditions min typ max unit sync timing requirements t ssync sync to the rising edge of clk setup time 0.3 ns t hsync sync to the rising edge of clk hold time 0.4 ns spi timing requirements t ds setup time between the data and th e rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high minimum period that sclk should be in a logic high state 10 ns t low minimum period that sclk should be in a logic low state 10 ns t en_sdio time required for the sdio pin to sw itch from an input to an output relative to the sclk falling edge 10 ns t dis_sdio time required for the sdio pin to switch from an o utput to an input relative to the sclk rising edge 10 ns timing diagrams clk+ clk? dco+ dco? cha3 chb3 cha4 chb4 cha5 d0+ to d13+ d0? to d13? t ch t clk t dco t pd t skew cha1 chb1 cha0 chb0 cha2 chb2 chb5 cha6 chb6 09635-002 figure 2. interleaved lvds mode data output timing t ssync t hsync sync clk+ 09635-016 figure 3. sync timing inputs
AD6649 rev. 0 | page 10 of 40 absolute maximum ratings table 6. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to agnd ?0.3 v to +2.0 v vin+a/vin+b, vin?a/vin?b to agnd ?0.3 v to avdd + 0.2 v clk+, clk? to agnd ?0.3 v to avdd + 0.2 v sync to agnd ?0.3 v to avdd + 0.2 v vcm to agnd ?0.3 v to avdd + 0.2 v csb to agnd ?0.3 v to drvdd + 0.3 v sclk to agnd ?0.3 v to drvdd + 0.3 v sdio to agnd ?0.3 v to drvdd + 0.3 v oeb to agnd ?0.3 v to drvdd + 0.3 v pdwn to agnd ?0.3 v to drvdd + 0.3 v d0?/d0+ through d13?/d13+ to agnd ?0.3 v to drvdd + 0.3 v fda/fdb to agnd ?0.3 v to drvdd + 0.3 v or+/or? to agnd ?0.3 v to drvdd + 0.3 v dco+/dco? to agnd ?0.3 v to drvdd + 0.3 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ?65c to +125c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. table 7. thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 unit 0 26.8 1.14 10.4 c/w 1.0 21.6 c/w 64-lead lfcsp 9 mm 9 mm (cp-64-4) 2.0 20.2 c/w 1 per jedec 51-7, plus jede c 25-5 2s2p test board. 2 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). 3 per mil-std 883, method 1012.1. 4 per jedec jesd51-8 (still air). typical ja is specified for a 4-layer pcb with solid ground plane. as shown in table 7 , airflow increases heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the ja . esd caution
AD6649 rev. 0 | page 11 of 40 pin configuration and fu nction descriptions 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d4? d4+ drvdd d5? d5+ d6? d6+ dco? dco+ d7? d7+ drvdd d8? d8+ d9? d9+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avdd avdd vin+b vin?b avdd avdd dnc vcm dnc dnc avdd avdd vin?a vin+a avdd avdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk+ clk? sync fda fdb dnc dnc d0? (lsb) d0+ (lsb) drvdd d1? d1+ d2? d2+ d3? d3+ notes 1. dnc = do not connect. do not connect to this pin. 2. the exposed thermal paddle on the bottom of the package provides the analog ground for the part. this exposed paddle must be connected to ground for proper operation. pdwn oeb csb sclk sdio or+ or? d13+ (msb) d13? (msb) d12+ d21? drvdd d11+ d11? d10+ d10? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD6649 top view (not to scale) 09635-004 pin 1 indicator figure 4. lfcsp interleaved parallel lvds pin configuration (top view) table 8. pin function descriptions (interleaved parallel lvds mode) pin no. mnemonic type description adc power supplies 10, 19, 28, 37 drvdd supply digital o utput driver supply (1.8 v nominal). 49, 50, 53, 54, 59, 60, 63, 64 avdd supply analog power supply (1.8 v nominal). 6, 7, 55, 56, 58 dnc do not connect. do not connect to this pin. 0 agnd, exposed paddle ground analog ground. the exposed thermal paddle on the bottom of the package provides the analog ground for the part. this exposed paddle must be connected to ground for proper operation. adc analog 51 vin+a input differential analog input pin (+) for channel a. 52 vin?a input differential analog input pin (?) for channel a. 62 vin+b input differential analog input pin (+) for channel b. 61 vin?b input differential analog input pin (?) for channel b. 57 vcm output common-mode level bias output for analog inputs. this pin should be decoupled to ground using a 0.1 f capacitor. 1 clk+ input adc clock inputtrue. 2 clk? input adc clock inputcomplement. adc fast detect outputs 4 fda output channel a fast detect indicator (cmos levels). 5 fdb output channel b fast detect indicator (cmos levels). digital input 3 sync input digital synchronization pin. slave mode only. digital outputs 9 d0+ (lsb) output channel a/channel b lvds output data 0true. 8 d0? (lsb) output channel a/channel b lvds output data 0complement. 12 d1+ output channel a/channel b lvds output data 1true. 11 d1? output channel a/channel b lvds output data 1complement. 14 d2+ output channel a/channel b lvds output data 2true. 13 d2? output channel a/channel b lvds output data 2complement. 16 d3+ output channel a/channel b lvds output data 3true.
AD6649 rev. 0 | page 12 of 40 pin no. mnemonic type description 15 d3? output channel a/channel b lvds output data 3complement. 18 d4+ output channel a/channel b lvds output data 4true. 17 d4? output channel a/channel b lvds output data 4complement. 21 d5+ output channel a/channel b lvds output data 5true. 20 d5? output channel a/channel b lvds output data 5complement. 23 d6+ output channel a/channel b lvds output data 6true. 22 d6? output channel a/channel b lvds output data 6complement. 27 d7+ output channel a/channel b lvds output data 7true. 26 d7? output channel a/channel b lvds output data 7complement. 30 d8+ output channel a/channel b lvds output data 8true. 29 d8? output channel a/channel b lvds output data 8complement. 32 d9+ output channel a/channel b lvds output data 9true. 31 d9? output channel a/channel b lvds output data 9complement. 34 d10+ output channel a/channel b lvds output data 10true. 33 d10? output channel a/channel b lvds output data 10complement. 36 d11+ output channel a/channel b lvds output data 11true. 35 d11? output channel a/channel b lvds output data 11complement. 39 d12+ output channel a/channel b lvds output data 12true. 38 d12? output channel a/channel b lvds output data 12complement. 41 d13+ (msb) output channel a/channel b lvds output data 13true. 40 d13? (msb) output channel a/channe l b lvds output data 13complement. 43 or+ output channel a/channe l b lvds overrangetrue. 42 or? output channel a/channel b lvds overrangecomplement. 25 dco+ output channel a/channel b lvds data clock outputtrue. 24 dco? output channel a/channel b lv ds data clock outputcomplement. spi control 45 sclk input spi serial clock. 44 sdio input/output spi se rial data input/output. 46 csb input spi chip select (active low). output enable and power-down 47 oeb input/output output enable input (active low). 48 pdwn input/output power-down input (active high). the operation of this pin depends on the spi mode and can be configured as power-down or standby (see table 14 ).
AD6649 rev. 0 | page 13 of 40 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, sample rate = 250 msps, dcs enabled, 1.75 v p-p differential input, vin = ?1.0 dbfs, 32k sample, t a = 25c, fixed-frequency nco, 95 mhz bw fir filter, unless otherwise noted. in the fft plots that follow, the location of the s econd and third harmonics is noted when they fall in the pass band of the filter. a ?1.0 dbfs input level at the analog inputs corres ponds to an output level of ?2.5 dbfs when using the fixed-frequency nco and 95 mhz fir filter. when using the tunable-frequency nco and 100 mhz fir filter, the output level is ?1.3 dbfs. these respective output level reductions are due to fir filter losses. see t he fir filters section for more details. 0 20 40 60 120 10 30 50 80 90 100 110 70 0 ?20 ?40 ?60 ?80 ?120 ?140 09635-112 amplitude (dbfs) frequency (mhz) ?100 f s = 250msps f in = 30.1mhz @ ?1.0dbfs snr = 72db (74.5dbfs) sfdr = 92dbc (in-band) third harmonic second harmonic figure 5. AD6649 single-tone fft with f in = 30.1 mhz 0 ?20 ?40 ?60 ?80 ?120 ?140 09635-113 amplitude (dbfs) ?100 f s = 250msps f in = 90.1mhz @ ?1.0dbfs snr = 71.6db (74.1dbfs) sfdr = 87.5dbc (in-band) third harmonic 0 20 40 60 120 10 30 50 80 90 100 110 70 frequency (mhz) second harmonic figure 6. AD6649 single-tone fft with f in = 90.1 mhz 0 ?20 ?40 ?60 ?80 ?120 ?140 09635-114 amplitude (dbfs) ?100 f s = 250msps f in = 140.1mhz @ ?1.0dbfs snr = 71.1db (73.6dbfs) sfdr = 85dbc (in-band) third harmonic 0 20 40 60 120 10 30 50 80 90 100 110 70 frequency (mhz) second harmonic figure 7. AD6649 single-tone fft with f in = 140.1 mhz 0 ?20 ?40 ?60 ?80 ?120 ?140 09635-215 amplitude (dbfs) ?100 f s = 250msps f in = 185.1mhz @ ?1.0dbfs snr = 70.5db (73.0dbfs) sfdr = 84.5dbc (in-band) third harmonic 0 20 40 60 120 10 30 50 80 90 100 110 70 frequency (mhz) figure 8. AD6649 single-tone fft with f in = 185.1 mhz 0 20 40 60 120 10 30 50 80 90 100 110 70 ?140 frequency (mhz) 0 ?20 ?40 ?60 ?80 ?120 09635-216 amplitude (dbfs) ?100 f s = 250msps f in = 220.1mhz @ ?1.0dbfs snr = 69.8db (72.3dbfs) sfdr = 84dbc (in-band) third harmonic second harmonic figure 9. AD6649 single-tone fft with f in = 220.1 mhz 0 ?20 ?40 ?60 ?80 ?120 ?140 09635-117 amplitude (dbfs) ?100 f s = 250msps f in = 305.1mhz @ ?1.0dbfs snr = 68.5db (71.0dbfs) sfdr = 83.5dbc (in-band) third harmonic 0 20 40 60 120 10 30 50 80 90 100 110 70 frequency (mhz) second harmonic figure 10. AD6649 single-tone fft with f in = 305.1 mhz
AD6649 rev. 0 | page 14 of 40 0 20 40 60 80 100 120 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 snr/sfdr (dbc and dbfs) input amplitude (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) sfdr (dbfs) 09635-118 figure 11. AD6649 single-tone snr/sfdr vs. input amplitude (a in ) with f in = 90.1 mhz 65 70 75 80 85 90 95 100 50 100 150 200 250 300 350 400 450 snr/sfdr (dbfs and dbc) input frequency (mhz) snr (dbfs) sfdr (dbc) 09635-119 figure 12. AD6649 single-tone snr/sfdr vs. input frequency (f in ) ?120 ?100 ?80 ?60 ?40 ?20 0 ?90.0 ?78.5 ?67.0 ?55.5 ?44.0 ?32.5 ?21.0 ?9.5 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 09635-120 figure 13. AD6649 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 89.12 mhz, f in2 = 92.12 mhz, f s = 250 msps ?120 ?100 ?80 ?60 ?40 ?20 0 ?90.0 ?78.5 ?67.0 ?55.5 ?44.0 ?32.5 ?21.0 ?9.5 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 09635-121 figure 14. AD6649 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184.12 mhz, f in2 = 187.12 mhz, f s = 250 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 010 30 60 amplitude (dbfs) frequency (mhz) 20 40 70 50 80 90 100 110 120 250msps 89.12mhz @ ?7.0dbfs 92.12mhz @ ?7.0dbfs sfdr = 88dbc (96.5dbfs) 09635-122 figure 15. AD6649 two-tone fft with f in1 = 89.12 mhz, f in2 = 92.12 mhz, f s = 250 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) 250msps 184.12mhz @ ?7.0dbfs 187.12mhz @ ?7.0dbfs sfdr = 85dbc (93.5dbfs) 09635-123 010 30 60 frequency (mhz) 20 40 70 50 80 90 100 110 120 figure 16. AD6649 two-tone fft with f in1 = 184.12 mhz, f in2 = 187.12 mhz, f s = 250 msps
AD6649 rev. 0 | page 15 of 40 70 75 80 85 90 95 100 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 snr/sfdr (dbfs/dbc) sample rate (msps) snr channel b (dbfs) sfdr channel b (dbc) snr channel a (dbfs) sfdr channel a (dbc) 09635-124 figure 17. AD6649 single-tone snr/sfdr vs. sample rate (f s ) with f in = 90.1 mhz 0 1000 2000 3000 4000 5000 6000 n ? 4 n ? 5 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 number of hits output code 1.32 lsb rms 16,378 total hits 09635-125 figure 18. AD6649 grounded input histogram
AD6649 rev. 0 | page 16 of 40 equivalent circuits v in avdd 09635-008 figure 19. equivalent analog input circuit 0.9v 15k ? 15k ? c lk+ clk? avdd avdd avdd 09635-009 figure 20. equivalent clock input circuit 0 9635-010 d r v dd dataout+ v? v+ dataout? v+ v? figure 21. equivalent lvds output circuit sdio 350? 26k ? drvdd 09635-011 figure 22. equivalent sdio circuit sclk or pdwn 350 ? 26k ? 09635-012 figure 23. equivalent sclk or pdwn input circuit csb 350 ? 26k ? a vdd 09635-014 figure 24. equivalent csb input circuit a vdd avdd 16k ? 0.9v 0.9v sync 09635-025 figure 25. equivalent sync input circuit
AD6649 rev. 0 | page 17 of 40 theory of operation the AD6649 has two analog input channels, two filter channels, and two digital output channels. the intermediate frequency (if) input signal passes through several stages before appearing at the output port(s) as a filtered and optionally decimated digital signal. the dual adc design can be used for diversity reception of signals, where the adcs operate identically on the same carrier but from two separate antennae. the adcs can also be operated with independent analog inputs. the user can sample frequencies from dc to 300 mhz using appropriate low-pass or band-pass filtering at the adc inputs with little loss in adc performance. operation to 400 mhz analog input is permitted but occurs at the expense of increased adc noise and distortion. synchronization capability is provided to allow synchronized timing between multiple devices. programming and control of the AD6649 are accomplished using a 3-pin spi-compatible serial interface. adc architecture the AD6649 architecture consists of a dual front-end sample- and-hold circuit, followed by a pipelined switched-capacitor adc. the quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched-capacitor digital- to-analog converter (dac) and an interstage residue amplifier (mdac). the mdac magnifies the difference between the recon- structed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or single- ended modes. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. during power-down, the output buffers go into a high impedance state. analog input considerations the analog input to the AD6649 is a differential switched- capacitor circuit that has been designed for optimum performance while processing a differential input signal. the clock signal alternatively switches the input between sample mode and hold mode (see the configuration shown in figure 26 ). when the input is switched into sample mode, the signal source must be capable of charging the sampling capacitors and settling within 1/2 clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low-pass filter at the adc input; therefore, the precise values are dependent on the application. in intermediate frequency (if) undersampling applications, the shunt capacitors should be reduced. in combination with the driving source impedance, the shunt capacitors limit the input bandwidth. refer to the an-742 application note , frequency domain response of switched-capacitor adcs ; the an-827 application note , a resonant approach to interfacing amplifiers to switched-capacitor adcs ; and the analog dialogue article, transformer-coupled front-end for wideband a/d converters , for more information on this subject. c par1 c par1 c par2 c par2 s s s s s s c fb c fb c s c s bias bias v in+ h v in? 09635-034 figure 26. switche d-capacitor input for best dynamic performance, the source impedances driving vin+ and vin? should be matched, and the inputs should be differentially balanced. input common mode the analog inputs of the AD6649 are not internally dc biased. in ac-coupled applications, the user must provide this bias externally. setting the device so that v cm = 0.5 avdd (or 0.9 v) is recommended for optimum performance. an on-board common-mode voltage reference is included in the design and is available from the vcm pin. using the vcm output to set the input common mode is recommended. optimum performance is achieved when the common-mode voltage of the analog input is set by the vcm pin voltage (typically 0.5 avdd). the vcm pin must be decoupled to ground by a 0.1 f capacitor, as described in the applications information section. this decoupling capacitor should be placed close to the pin to minimize the series resistance and inductance between the part and this capacitor.
AD6649 rev. 0 | page 18 of 40 differential input configurations optimum performance is achieved while driving the AD6649 in a differential input configuration. for baseband applications, the ad8138, ada4937-2 , ada4938-2 , and ada4930-2 differential drivers provide excellent performance and a flexible interface to the adc. the output common-mode voltage of the ada4930-2 is easily set with the vcm pin of the AD6649 (see figure 27 ), and the driver can be configured in a sallen-key filter topology to provide band-limiting of the input signal. v in 76.8 ? 120 ? 0.1f 200? 200? 90 ? 33? 33? 15? 15? 5pf 15p f 0.1f 15pf 33? adc vin? vin+ vcm ada4930-2 09635-039 figure 27. differential input configuration using the ada4930-2 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration. an example is shown in figure 28 . to bias the analog input, the vcm voltage can be connected to the center tap of the secondary winding of the transformer. 2v p-p 49.9 ? 0.1f r1 r1 c1 adc vin+ vin? vcm c2 r2 r3 r2 c2 09635-040 r3 0.1f 33? figure 28. differential transformer-coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz. excessive signal power can also cause core saturation, which leads to distortion. at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the AD6649. for applications where snr is a key parameter, differential double balun coupling is the recommended input configuration (see figure 30 ). in this configuration, the input is ac-coupled and the cml is provided to each input through a 33 resistor. these resistors compensate for losses in the input baluns to provide a 50 impedance to the driver. in the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input fre- quency and source impedance. based on these parameters the value of the input resistors and capacitors may need to be adjusted or some components may need to be removed. table 9 displays recommended values to set the rc network for different input frequency ranges. however, these values are dependent on the input signal and bandwidth and should be used only as a starting guide. note that the values given in table 9 are for each r1, r2, c2, and r3 component shown in figure 28 and figure 30 . table 9. example rc network frequency range (mhz) r1 series () c1 differential (pf) r2 series () c2 shunt (pf) r3 shunt () 0 to 100 33 8.2 0 15 49.9 100 to 250 15 3.9 0 8.2 49.9 an alternative to using a transformer-coupled input at frequencies in the second nyquist zone is to use an amplifier with variable gain. the ad8375 or ad8376 digital variable gain amplifier (dvgas) provides good performance for driving the AD6649. figure 29 shows an example of the ad8376 driving the AD6649 through a band-pass antialiasing filter. ad8376 AD6649 1h 1h 1nf 1nf vpos vcm 15pf 68nh 2.5k ?U 2pf 301 ? 165? 165? 5.1pf 3.9pf 180nh 1000pf 1000pf notes 1. all inductors are coilcraft ? 0603cs components with the exception of the 1h choke inductors (coilcraft 0603ls). 2. filter values shown are for a 20mhz bandwidth filter centered at 140mhz. 180nh 220nh 220nh 09635-115 figure 29. differential input configuration using the ad8376 adc r1 0.1f 0.1f 2 v p- p vin+ vin? vcm c1 r1 r2 r2 0.1f s 0.1f 33? 33? s p a p 09635-041 c2 r3 c2 r3 0.1f 33? figure 30. differential double balun input configuration
AD6649 rev. 0 | page 19 of 40 voltage reference a stable and accurate voltage reference is built into the AD6649. the full-scale input range can be adjusted by varying the reference voltage via spi. the input span of the adc tracks reference voltage changes linearly. clock input considerations for optimum performance, the AD6649 sample clock inputs, clk+ and clk?, should be clocked with a differential signal. the signal is typically ac-coupled into the clk+ and clk? pins via a transformer or via capacitors. these pins are biased internally (see figure 31 ) and require no external bias. if the inputs are floated, the clk? pin is pulled low to prevent spurious clocking. avdd clk+ 4pf 4pf clk? 0.9v 09635-044 figure 31. simplified equivalent clock input circuit clock input options the AD6649 has a very flexible clock input structure. clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 32 and figure 33 show two preferable methods for clocking the AD6649 (at clock rates of up to 625 mhz). a low jitter clock source is converted from a single-ended signal to a differential signal using an rf balun or rf transformer. the rf balun configuration is recommended for clock frequencies between 125 mhz and 625 mhz, and the rf transformer is recom- mended for clock frequencies from 10 mhz to 200 mhz. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the AD6649 to approximately 0.8 v p-p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD6649 while preserving the fast rise and fall times of the signal, which are critical to low jitter performance. 390pf 390pf 390pf schottky diodes: hsms2822 clock input 50? 100 ? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1z xfmr 0 9635-048 figure 32. transformer-coupled differential clock (up to 200 mhz) 390pf 390pf 390pf clock input 25? 25? clk? clk+ schottky diodes: hsms2822 adc 09635-049 figure 33. balun-coupled differential clock (up to 625 mhz) if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins as shown in figure 34 . the ad9510 , ad9511 , ad9512 , ad9513 , ad9514 , ad9515 , ad9516 , ad9517 , ad9518 , ad9520 , ad9522 , ad9523 , ad9524 , and adclk905/adclk907/adclk925 clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? pecl driver 50k ? 50k? clk? clk+ clock input clock input ad95xx adc 09635-050 figure 34. differential pecl sample clock (up to 625 mhz) a third option is to ac-couple a differential lvds signal to the sample clock input pins, as shown in figure 35 . the ad9510 , ad9511 , ad9512 , ad9513 , ad9514 , ad9515 , ad9516 , ad9517 , ad9518 , ad9520 , ad9522, ad9523 , and ad9524 clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 50k? 50k ? clk? clk+ c loc k input c loc k input ad95xx lvds driver adc 09635-051 figure 35. differential lvds sample clock (up to 625 mhz) input clock divider the AD6649 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. the duty cycle stabilizer (dcs) is enabled by default on power-up. the AD6649 clock divider can be synchronized using the external sync input. bit 1 and bit 2 of register 0x3a allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchro- nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling.
AD6649 rev. 0 | page 20 of 40 clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD6649 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD6649. jitter on the rising edge of the input clock is still of paramount concern and is not reduced by the duty cycle stabilizer. the duty cycle control loop does not function for clock rates less than 40 mhz nominally. the loop has a time constant associated with it that must be considered when the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the time period that the loop is not locked, the dcs loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the duty cycle stabilizer. in all other applications, enabling the dcs circuit is recommended to maximize ac performance. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f in ) due to jitter (t j ) can be calculated by snr hf = ?10 log[(2 f in t jrms ) 2 + 10 ] )10/( lf snr ? in the equation, the rms aperture jitter represents the root- mean-square of all jitter sources, which include the clock input, the analog input signal, and the adc aperture jitter specification. if undersampling applications are particularly sensitive to jitter, as shown in figure 36 . 50 55 60 65 70 75 80 11 01 0 0 input frequency (mhz) 1000 snr (dbfs) 0.05ps 0.20ps 0.50ps 1.00ps 1.50ps measured 09635-140 figure 36. snr (95 mhz bw) vs. input frequency and jitter the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD6649. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. refer to the an-501 application note , aperture uncertainty and adc system performance , and the an-756 application note , sampled systems and the effects of clock phase noise and jitter , for more information about jitter performance as it relates to adcs. power dissipation and standby mode as shown in figure 37 , the power dissipated by the AD6649 is proportional to its sample rate. the data in figure 37 was taken using the same operating conditions as those used for the typical performance characteristics . 0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 40 60 80 100 120 140 160 180 200 220 250 supply current (a) total power (w) encode frequency (msps) i avdd i drvdd total power 09635-037 figure 37. AD6649 power and current vs. sample rate by asserting pdwn (either through the spi port or by asserting the pdwn pin high), the AD6649 is placed in power-down mode. in this state, the adc typically dissipates 10 mw. during power-down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the AD6649 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. as a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. when using the spi port interface, the user can place the adc in power-down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. see the memory map register description section and the an-877 application note , interfacing to high speed adcs via spi , for additional details.
AD6649 rev. 0 | page 21 of 40 digital outputs the AD6649 output drivers can be configured for either ansi lvds or reduced drive lvds using a 1.8 v drvdd supply. as detailed in the an-877 application note , interfacing to high speed adcs via spi , the data format can be selected for offset binary, twos complement, or gray code when using the spi control. digital output enable function (oeb) the AD6649 has a flexible three-state ability for the digital output pins. the three-state mode is enabled using the oeb pin or through the spi interface. if the oeb pin is low, the output data drivers are enabled. if the oeb pin is high, the output data drivers are placed in a high impedance state. this oeb function is not intended for rapid access to the data bus. note that oeb is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. when using the spi interface, the data and fast detect outputs of each channel can be independently three-stated by using the output enable bar bit (bit 4) in register 0x14. because the output data is interleaved, if only one of the two channels is disabled, the data of the remaining channel is repeated in both the rising and falling output clock cycles. timing the AD6649 provides latched data with a pipeline delay of 23 or 43 input sample clock cycles, depending on the mode of operation. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. the length of the output data lines and loads placed on them should be minimized to reduce transients within the AD6649. these transients can degrade converter dynamic performance. the lowest typical conversion rate of the AD6649 is 40 msps. at clock rates below 40 msps, dynamic performance may degrade. data clock output (dco) the AD6649 also provides data clock output (dco) intended for capturing the data in an external register. figure 2 shows a graphical timing diagram of the AD6649 output modes. table 10. output data format input (v) vin+ ? vin?, input span = 1.75 v p-p (v) offset binary output mode twos complement mode (default) or vin+ ? vinC +0.875 11 1111 1111 1111 01 1111 1111 1111 1
AD6649 rev. 0 | page 22 of 40 digital processing the AD6649 includes a digital processing section that provides filtering. this digital processing section includes a numerically controlled oscillator (nco), a selectable fir filter (high perfor- mance or low latency), and a second coarse nco (f s /4 fixed value) for output frequency translation (complex to real). these blocks can be configured in several modes to implement a signal processing function. refer to figure 1 for the functional block diagram of the AD6649. numerically controlled oscillator (nco) frequency translation is accomplished with an nco shared between the two channels. amplitude and phase dither can be enabled on chip to improve the noise and spurious performance of the nco. because the filtering prevents usage of part of the nyquist spectrum, a means is needed to translate the sampled input spectrum into the usable range of the decimation filter. to achieve this, a 32-bit, tuning, complex nco is provided. this nco/mixer allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. when using the low latency fir, the nco must be tuned to f s /4 (0x40000000). this prevents unwanted aliases from falling back into the band of interest. nco and fir filter modes the nco and fir blocks can be used in two modes depending on the bandwidth and latency requirement of the application. the two modes of operation of these blocks are summarized in table 11 . table 11. signal path modes mode fir output bandwidth at 245.76 msps fixed-frequency nco, 95 mhz fir filter low latency (default) 95 mhz tunable-frequency nco, 100 mhz fir filter high performance 99.5 mhz two fixed-coefficient fir filters provide filtering capability. a low latency fir or a high performance fir can be selected. it removes the negative frequency images to avoid aliasing negative frequencies for real outputs. figure 38 , figure 39 , and figure 40 show the progression of a 95 mhz bandwidth signal through the filter stages when using the fixed-frequency nco and 95 mhz fir filter with a sample rate of 245.76 msps. the tunable-frequency nco can be used instead and operates in a similar fashion. in these modes, the output is centered at 61.44 mhz, assuming a 245.76 msps sample rate. f s /4 fixed-frequency nco a fixed-frequency f s /4 nco is provided to translate the filtered, decimated signal from dc to f s /4 to allow a real output. the f s /4 nco is required in all operation modes because complex output from the part is not supported. real adc input 122.88 61.44 108.94 13.94 0 ?61.44 ?108.94 ?13.94 09635-042 figure 38. example AD6649 real 95 mhz bandwidth input signal centered at 61.44 mhz (f adc = 245.76 mhz) complex adc output/nco output ?122.88 122.88 ?75.38 75.38 ?47.5 47.5 0 09635-043 figure 39. example AD6649 95 mhz bandwidth input signal tuned to dc using the nco (nco frequency = 61.44 mhz) tuned nco output 122.88 13.940 108.94 61.44 09635-247 figure 40. example AD6649 95 mhz ba ndwidth output signal tuned to f s /4 (nco frequency = 61.44 mhz)
AD6649 rev. 0 | page 23 of 40 numerically controlled oscillator (nco) frequency translation this processing stage comprises a digital tuner consisting of a 32-bit complex numerically controlled oscillator (nco). the nco is always enabled. this nco block accepts a real input from the adc stage and outputs a frequency translated complex (i and q) output. the nco frequency is programmed in register 0x52 through register 0x55. these four 8-bit registers make up a 32-bit unsigned frequency programming word. frequencies between ?clk/2 and +clk/2 are represented using the following frequency words: ? 0x80000000 represents a frequency given by ?clk/2. ? 0x00000000 represents dc (frequency = 0 hz). ? 0x7fffffff represents clk/2 ? clk/2 32 . use the following equation to calculate the nco frequency: clk clk f ffmod nco_freq ),( 2 32 = where: nco_freq is a 32-bit twos complement number representing the nco frequency register. f is the desired carrier frequency in hertz. f clk is the AD6649 adc clock rate in hertz. nco synchronization the AD6649 ncos within a single part or across multiple parts can be synchronized using the external sync input. bit 0 and bit 1 of register 0x58 allow the nco to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the nco to restart at the programmed phase offset value. nco amplitude and phase dither the nco block contains amplitude and phase dither to improve the spurious performance. amplitude dither improves perfor- mance by randomizing the amplitude quantization errors within the angular-to-cartesian conversi on of the nco. this option reduces spurs at the expense of a slightly raised noise floor. with amplitude dither enabled, the nco has an snr of greater than 93 db and an sfdr of greater than 115 db. with amplitude dither disabled, the snr is increased to greater than 96 db at the cost of sfdr performance, which is reduced to 100 db. the nco amplitude and phase dither are recommended and can be enabled by setting bit 1 and bit 2 in register 0x51.
AD6649 rev. 0 | page 24 of 40 fir filters the two fir filters that can be used are either a 47-tap, high performance, fixed-coefficient fir filter or a 21-tap, low latency, fixed-coefficient fir filter. these filters are useful in providing alias protection at the device output. the high performance fir is a simple sum-of-products fir filter with 47 filter taps and 21-bit fixed coefficients. note that this filter does not decimate. the normalized coefficients used in the implementation and the decimal equivalent value of the coefficients are listed in table 12 . table 12. high performance fir filter coefficients coefficient number normalized coefficient decimal coefficient (21-bit) c0, c46 ?0.0001335 ?140 c1, c45 ?0.0009689 ?1016 c2, c44 ?0.0024185 ?2536 c3, c43 ?0.0019341 ?2028 c4, c42 0.0023584 2473 c5, c41 0.0051260 5375 c6, c40 ?0.0009680 ?1015 c7, c39 ?0.0086231 ?9042 c8, c38 ?0.0011368 ?1192 c9, c37 0.0142097 14900 c10, c36 0.0064697 6784 c11, c35 ?0.0207596 ?21768 c12, c34 ?0.0161047 ?16887 c13, c33 0.0274601 28794 c14, c32 0.0310631 32572 c15, c31 ?0.0348339 ?36526 c16, c30 ?0.0557785 ?58488 c17, c29 0.0415993 43620 c18, c28 0.0986786 103472 c19, c27 ?0.0463982 ?48652 c20, c26 ?0.1893501 ?198548 c21, c25 0.0505829 53040 c22, c24 0.6113434 641040 c23 0.9171314 961682 fir synchronization the AD6649 filters within a single part or across multiple parts can be synchronized using the external sync input. the filters can be configured to be resynchronized on every sync signal or only on the first sync signal after the spi control register is written. a valid sync causes the fir filter to restart at the programmed decimation phase value. bit 4 and bit 5 of register 0x58 allow the fir to be resynchronized on every sync signal or only on the first sync signal after the register is written. filter performance when using the fixed-frequency nco and a 95 mhz fir filter, the output rate is equal to the sample clock rate. the composite response of this mode is shown in figure 41 . the detailed pass- band response for this mode is shown in figure 42 . to place the part in this mode, set spi register 0x50 to 0xb0. when operating in this mode, the nco must be placed at f s /4, and the low latency nco select bit (bit 0) in register 0x5a must be set. it is important to note that a ?1.0 dbfs input level at the analog inputs corresponds to an output level of ?2.5 dbfs when using the low latency fir filter. this output level reduction is a result of the ?1.5 db pass- band attenuation in the fir filter in this mode and does not result in loss in the dynamic range of the converter. 0 ?1 ?2 ?3 ?4 0 30.72 61.44 92.16 122.88 09635-144 amplitude (dbc) filter response (mhz) figure 41. low latency fir filter co mposite response at 245.76 msps (fixed-frequency nco, 95 mhz fir filter mode) ? 1.000 ?1.125 ?1.250 ?1.375 ?1.500 0 30.72 61.44 92.16 122.88 09635-145 amplitude (dbc) filter response (mhz) figure 42. low latency fir filter pass-band response at 245.76 msps (fixed-frequency nco, 95 mhz fir filter mode) when using the tunable-frequency nco and 100 mhz fir filter, the output rate is equal to the sample clock rate. the response of the high performance fir filter is shown in figure 43 . the detailed pass-band response for this mode is shown in figure 44 . to place the part into this mode, set spi register 0x50 to 0xa0. when using the high performance fir filter, the output level is ?1.3 dbfs for a corresponding input level of ?1.0 dbfs at the analog inputs. this is a result of the ?0.3 db pass-band attenuation of the fir filter in this mode and does not result in loss in the dynamic range of the converter.
AD6649 rev. 0 | page 25 of 40 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 30.72 61.44 92.16 122.88 09635-146 amplitude (dbc) filter response (mhz) figure 43. high performance fir filter pass-band response at 245.76 msps (tunable-frequency nco, 100 mhz fir filter) 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?0.7 ?0.8 ?0.9 ?1.0 0 15.36 30.72 46.08 61.44 09635-147 amplitude (dbc) filter response (mhz) figure 44. high performance fir filter pass-band response at 245.76 msps (tunable-frequency nco, 100 mhz fir filter) output nco the output of the 32-bit fine-tuning nco is complex and typically centered in frequency around dc. this complex output is carried through the stages of either the 95 mhz or 100 mhz fir filter to provide proper antialiasing filtering. the final nco provides a means to move this complex output signal away from dc so that a real output can be provided from the AD6649. the output nco translates the output from dc to a frequency equal to the output frequency divided by 4 (f s /4). this provides the user with an output signal centered at f s /4 in frequency. the AD6649 output ncos within a single part or across multiple parts can be synchronized using the external sync input. bit 7 and bit 6 of register 0x58 allow the output nco to be resynchronized on every sync signal or only on the first sync signal after the register is written.
AD6649 rev. 0 | page 26 of 40 adc overrange and gain control in receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. the standard overflow indicator provides delayed information on the state of the analog input that is of limited value in preventing clipping. therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip occurs. in addition, because input signals can have significant slew rates, latency of this function is of concern. using the spi port, the user can provide a threshold above which the fd output is active. bit 0 of spi register 0x45 allows the user to select the threshold level. as long as the signal is below the selected threshold, the fd output remains low. in this mode, the magnitude of the data is considered in the calculation of the condition, but the sign of the data is not considered. the threshold detection responds identically to positive and negative signals outside the desired range (magnitude). adc overrange (or) the adc overrange indicator is asserted when an overrange is detected on the input of the adc. the overrange condition is determined at the output of the adc pipeline and, therefore, is subject to a latency of 7 adc clock cycles. an overrange at the input is indicated by this bit 7 clock cycles after it occurs. gain switching the AD6649 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging amplifiers are employed. this circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed. one such use is to detect when an adc is about to reach full scale with a particular input cond ition. the result is to provide an indicator that can be used to quickly insert an attenuator that prevents adc overdrive. fast threshold detection (fda and fdb) the fd indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold register, located in register 0x47 and register 0x48. the selected threshold register is compared with the signal magnitude at the output of the adc. the fast upper threshold detection has a latency of 4 clock cycles. the upper threshold magnitude is defined by the following equation: upper threshold magnitude (dbfs) = 20 log( threshold magnitude /2 13 ) the fd indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. the lower threshold is programmed in the fast detect lower threshold register, located at register 0x49 and register 0x4a. the fast detect lower threshold register is a 15-bit register that is compared with the signal magnitude at the output of the adc. this comparison is subject to the adc pipeline latency but is accurate in terms of converter resolution. the lower threshold magnitude is defined by the following equation: lower threshold magnitude (dbfs) = 20 log( threshold magnitude /2 13 ) the dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time register, located in register 0x4b and register 0x4c. the operation of the upper threshold and lower threshold registers, along with the dwell time, is shown in figure 45 . upper threshold lower threshold fda or fdb midscale dwell time timer reset by rise above lt timer completes before signal rises above lt dwell time 09635-148 figure 45. threshold settings for fda and fdb signals
AD6649 rev. 0 | page 27 of 40 dc correction because the dc offset of the adc may be significantly larger than the signal being measured, a dc correction circuit is included to null the dc offset before measuring the power. the dc correction circuit can also be switched into the main signal path, but this may not be appropriate if the adc is digitizing a time-varying signal with significant dc content, such as gsm. dc correction bandwidth the dc correction circuit is a high-pass filter with a program- mable bandwidth (ranging between 0.29 hz and 2.387 khz at 245.76 msps). the bandwidth is controlled by writing the 4-bit dc correction bandwidth select register, located at register 0x40, bits[5:2]. the following equation can be used to compute the bandwidth value for the dc correction circuit: = ?? 2 2__ 14 clk k f bwcorrdc where: k is the 4-bit value programmed in bits[5:2] of register 0x40 (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). f clk is the AD6649 adc sample rate in hertz. dc correction readback the current dc correction value can be read back in register 0x41 and register 0x42 for each channel. the dc correction value is a 16-bit value that can span the entire input range of the adc. dc correction freeze setting bit 6 of register 0x40 freezes the dc correction at its current state and continues to use the last updated value as the dc correction value. clearing this bit restarts dc correction and adds the currently calculated value to the data. dc correction enable bits setting bit 1 of register 0x40 enables dc correction for use in the output data signal path.
AD6649 rev. 0 | page 28 of 40 channel/chip synchronization the AD6649 has a sync input that allows the user flexible syn- chronization options for synchronizing the internal blocks. the sync feature is useful for guaranteeing synchronized operation across multiple adcs. the input clock divider, nco, fir filters, and the output f s /4 nco can be synchronized using the sync input. each of these blocks can be enabled to synchronize on a single occurrence of the sync signal or on every occurrence by setting the appropriate bits in register 0x58. the sync input is internally synchronized to the sample clock. however, to ensure that there is no timing uncertainty between multiple parts, the sync input signal should be synchronized to the input clock signal. the sync input should be driven using a single-ended cmos type signal. if bit 1 in register 0x59 is used, the sync input can be set to either level or edge sensitive mode. if the sync input is set to edge sensitive mode, bit 0 of register 0x59 can be used to determine whether the rising or falling edge is used.
AD6649 rev. 0 | page 29 of 40 serial port interface (spi) the AD6649 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields. these fields are documented in the memory map section. for detailed operational information, see the an-877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin, the sdio pin, and the csb pin (see table 13 ). the sclk (serial clock) pin is used to synchronize the read and write data presented from/to the adc. the sdio (serial data input/output) pin is a dual-purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb (chip select bar) pin is an active low control that enables or disables the read and write cycles. table 13. serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write cycles. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 46 and table 5 . other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the cs b can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. all data is composed of 8-bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued. this allows the serial data input/output (sdio) pin to change direction from an input to an output. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the serial data input/ output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb first mode or in lsb first mode. msb first is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see the an-877 application note , interfacing to high speed adcs via spi . hardware interface the pins described in table 13 comprise the physical interface between the user programming device and the serial port of the AD6649. the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an-812 application note , micro- controller-based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6649 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods.
AD6649 rev. 0 | page 30 of 40 spi accessible features table 14 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an-877 application note , interfacing to high speed adcs via spi . the AD6649 part-specific features are described in the memory map register description section. table 14. features accessible using the spi feature name description mode allows the user to set either power-down mode or standby mode clock allows the user to access the dcs via the spi offset allows the user to digita lly adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set up outputs output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay vref allows the user to set the reference voltage digital processing allows the user to enable the ncos, fir filters, and synchronization features don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 09635-079 figure 46. serial port interface timing diagram
AD6649 rev. 0 | page 31 of 40 memory map reading the memory map register table each row in the memory map register table has eight bit locations. the memory map is roughly divided into four sections: the chip configuration registers (address 0x00 to address 0x02); the channel index and transfer registers (address 0x05 and address 0xff); the adc functions registers, including setup, control, and test (address 0x08 to address 0x3a); and the digital feature control registers (address 0x40 to address 0x5a). the memory map register table (see table 15 ) documents the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x14, the output mode register, has a hexadecimal default value of 0x05. this means that bit 0 = 1 and the remaining bits are 0s. this setting is the default output format value, which is twos complement. for more information on this function and others, see the an-877 application note , interfacing to high speed adcs via spi . this document details the functions controlled by register 0x00 to register 0x25. the remaining registers, from register 0x3a to register 0x5a, are documented in the memory map register description section. open and reserved locations all address and bit locations that are not included in table 15 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), this address location should not be written. default values after the AD6649 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 15 . logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x08 to address 0x20, address 0x3a, address 0x40 to address 0x42, address 0x45 to 0x4c, and address 0x50 to address 0x5a are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allows these registers to be updated internally and simultaneously when the transfer bit is set. the internal update takes place when the transfer bit is set, and then the bit autoclears. channel-specific registers some channel setup functions, such as the signal monitor thresh- olds, can be programmed to a different value for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 15 as local. these local registers and bits can be accessed by setting the appropriate channel a or channel b bits in register 0x05. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, only channel a or channel b should be set to read one of the two registers. if both bits are set during an spi read cycle, the part returns the value for channel a. registers and bits designated as global in table 15 affect the entire part and the channel features for which independent settings are not allowed between channels. the settings in register 0x05 do not affect the global registers and bits.
AD6649 rev. 0 | page 32 of 40 memory map register table all address and bit locations that are not included in table 15 are not currently supported for this device. table 15. memory map registers addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configurati on registers 0x00 spi port configuration (global) 1 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles are mirrored so that lsb first mode or msb first mode registers correctly, regardless of shift mode. 0x01 chip id (global) 8-bit chip id[7:0] (AD6649 = 0xa1) (default) 0xa1 read only. 0x02 chip grade (global) open open speed grade id 00 = 250 msps open open open open speed grade id used to differentiate devices; read only. channel index and transfer registers 0x05 channel index (global) open open open open open open adc b (default) adc a (default) 0x03 bits are set to determine which device on the chip receives the next write command; applies to local registers only. 0xff transfer (global) open open open open open open open transfer 0x00 synchro- nously transfers data from the master shift register to the slave. adc functions 0x08 power modes (local) open open external power- down pin function (local) 0 = power- down 1 = standby open open open internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = reserved 0x00 determines various generic modes of chip operation. 0x09 global clock (global) open open open ope n open open open duty cycle stabilizer (default) 0x01 0x0b clock divide (global) open open input clock di vider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 clock divide values other than 000 auto- matically cause the duty cycle stabilizer to become active.
AD6649 rev. 0 | page 33 of 40 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x0d test mode (local) user test mode control 0 = con- tinuous/ repeat pattern 1 = single pattern, then 0s open reset pn long gen reset pn short gen output test mode 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn long sequence 0110 = pn short sequence 0111 = one/zero word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output 0x00 when this register is set, the test data is placed on the output pins in place of normal data. 0x0e bist enable (local) open open open open open reset bist sequence open bist enable 0x00 0x10 offset adjust (local) open open offset adjust in lsbs from +31 to ?32 (twos complement format) 0x00 0x14 output mode open open open output enable bar (local) open output invert (local) 1 = normal (default) 0 = inverted output format 00 = offset binary 01 = twos complement (default) 10 = gray code 11 = reserved (local) 0x05 configures the outputs and the format of the data. 0x15 output adjust (global) open open open open lv ds output drive current adjust 0000 = 3.72 ma output drive current 0001 = 3.5 ma output drive current (default) 0010 = 3.30 ma output drive current 0011 = 2.96 ma output drive current 0100 = 2.82 ma output drive current 0101 = 2.57 ma output drive current 0110 = 2.27 ma output drive current 0111 = 2.0 ma output drive current (reduced range) 1000 to 1111 = reserved 0x01 0x16 clock phase control (global) invert dco clock open open open open ope n open open 0x00 0x17 dco output delay (global) enable dco clock delay open open dco clock delay [delay = (3100 ps regi ster value/31 +100)] 00000 = 100 ps 00001 = 200 ps 00010 = 300 ps 11110 = 3100 ps 11111 = 3200 ps 0x00 0x18 input span select (global) open open open full-scale in put voltage selection 01111 = 2.087 v p-p 00001 = 1.772 v p-p 00000 = 1.75 v p-p (default) 11111 = 1.727 v p-p 10000 = 1.383 v p-p 0x00 full-scale input adjustment in 0.022 v steps. 0x19 user test pattern 1 lsb (global) user test pattern 1[7:0] 0x00 0x1a user test pattern 1 msb (global) user test pattern 1[15:8] 0x00 0x1b user test pattern 2 lsb (global) user test pattern 2[7:0] 0x00 0x1c user test pattern 2 msb (global) user test pattern 2[15:8] 0x00 0x1d user test pattern 3 lsb (global) user test pattern 3[7:0] 0x00 0x1e user test pattern 3 msb (global) user test pattern 3[15:8] 0x00
AD6649 rev. 0 | page 34 of 40 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x1f user test pattern 4 lsb (global) user test pattern 4[7:0] 0x00 0x20 user test pattern 4 msb (global) user test pattern 4[15:8] 0x00 0x24 bist signature lsb (local) bist signature[7:0] 0x00 read only. 0x25 bist signature msb (local) bist signature[15:8] 0x00 read only. 0x3a sync control (global) open open open open open clock divider next sync only clock divider sync enable master sync buffer enable 0x00 digital feature control registers 0x40 dc correction control (local) open dc correction freeze dc correction bandwidth select 0000 = 2387.32 hz 0001 = 1193.66 hz 0010 = 596.83 hz 0011 = 298.42 hz 0100 = 149.21 hz 0101 = 74.60 hz 0110 = 37.30 hz 0111 = 18.65 hz 1000 = 9.33 hz 1001 = 4.66 hz 1010 = 2.33 hz 1011 = 1.17 hz 1100 = 0.58 hz 1101 = 0.29 hz 1110 = reserved 1111 = reserved dc correction enable open 0x00 0x41 dc correction value 0 (local) dc correction value[7:0] read only. 0x42 dc correction value 1 (local) dc correction value[15:8] read only. 0x45 fast detect control (local) open open open open force fd output enable force fd output value reserved enable fast detect output 0x00 0x47 fast detect upper threshold 0 (local) fast detect upper threshold[7:0] 0x00 0x48 fast detect upper threshold 1 (local) open open open fast detect u pper threshold[12:8] 0x00 0x49 fast detect lower threshold 0 (local) fast detect lower threshold[7:0] 0x00 0x4a fast detect lower threshold 1 (local) open open open fast detect lo wer threshold[12:8] 0x00 0x4b fast detect dwell time 0 (local) fast detect dwell time[7:0] 0x00 0x4c fast detect dwell time 1 (local) fast detect dwell time[15:8] 0x00 0x50 filter control (local) 1 reserved 1 fir mode 0 = high perfor- mance 1 = low latency output gain 0 = 0 db 1 = ?6 db 9-bit output mode enable datapath gain 00 = 0 db 01 = ?6 db 10 = ?12 db 11 = ?18 db 0xb0
AD6649 rev. 0 | page 35 of 40 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x51 nco control (local) reserved nco32 to f s /4 nco sync enable spectral reversal 1 reserved nco32 amplitude dither enable nco32 phase dither enable 1 0x51 0x52 nco frequency 3 (local) nco frequency value[31:24] 0x40 0x53 nco frequency 2 (local) nco frequency value[23:16] 0x00 0x54 nco frequency 1 (local) nco frequency value[15:8] 0x00 0x55 nco frequency 0 (local) nco frequency value[7:0] 0x00 0x56 nco phase offset 1 (local) nco phase value[15:8] 0x00 0x57 nco phase offset 0 (local) nco phase value[7:0] 0x00 0x58 sync control (local) f s /4 nco next sync only f s /4 nco sync enable fir next sync only fir sync enable reserved reserved nco32 next sync only nco32 sync enable 0x00 0x59 sync pin control (local) open open open open open open sync pin sensitivity 0 = sync on high level 1 = sync on edge sync pin edge sensitivity 0 = sync on falling edge 1 = sync on rising edge 0x00 0x5a nco control 2 (local) open open open ope n open open open low latency nco select 0x01 1 the channel index register at address 0x05 should be set to 0x03 (default) when writing to address 0x00.
AD6649 rev. 0 | page 36 of 40 memory map register description for more information on functions controlled in register 0x00 to register 0x25, see the an-877 application note , interfacing to high speed adcs via spi . sync control (register 0x3a) bits73reserved bit 2clock divider next sync only if the master sync buffer enable bit (address 0x3a, bit 0) and the clock divider sync enable bit (address 0x3a, bit 1) are high, bit 2 allows the clock divider to sync to the first sync pulse that it receives and to ignore the rest. the clock divider sync enable bit (address 0x3a, bit 1) resets after it syncs. bit 1clock divider sync enable bit 1 gates the sync pulse to the clock divider. the sync signal is enabled when bit 1 is high and bit 0 is high. this is continuous sync mode. bit 0master sync buffer enable bit 0 must be set high to enable any of the sync functions. if the sync capability is not used, this bit should remain low to conserve power. dc correction control (register 0x40) bit 7reserved bit 6dc correction freeze when bit 6 is set high, the dc correction is no longer updated to the signal monitor block, which holds the last dc value calculated. bits[5:2]dc correction bandwidth select bits[5:2] set the averaging time of the signal monitor dc correction function. this 4-bit word sets the bandwidth of the correction block, according to the following equation: = ?? 2 2__ 14 clk k f bwcorrdc where: k is the 4-bit value programmed in bits[5:2] of register 0x40 (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). f clk is the AD6649 adc sample rate in hertz. bit 1dc correction enable setting this bit high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path. bit 0reserved fast detect control (register 0x45) bits74reserved bit 3force fd output enable setting this bit high forces the fd output pin to the value written to bit 2 of this register (register 0x45). this enables the user to force a known value on the fd pin for debugging. bit 2force fd output value the value written to bit 2 is forced on the fd output pin when bit 3 is written high. bit 1reserved bit 0enable fast detect output setting this bit high enables the output of the upper threshold fd comparator to drive the fd output pin. fast detect upper threshold (register 0x47 and register 0x48) register 0x48 bits75reserved register 0x48 bits40fast detect upper threshold128 register 0x47 bits70fast detect upper threshold70 these registers provide an upper limit threshold. the 13-bit value is compared with the output magnitude from the adc block. if the adc magnitude exceeds this threshold value, the fd output pin is set if bit 0 in register 0x45 is set. fast detect lower threshold (register 0x49 and register 0x4a) register 0x4a bits75reserved register 0x4a bits40fast detect lower threshold128 register 0x49 bits70fast detect lower threshold70 these registers provide a lower limit threshold. the 13-bit value is compared with the output magnitude from the adc block. if the adc magnitude is less than this threshold value for the number of cycles programmed in the dwell time register, the fd output bit is cleared. fast detect dwell time (register 0x4b and register 0x4c) register 0x4c bits70fast detect dwell time158 register 0x4b bits70fast detect dwell time70 these register values set the minimum time in adc sample clock cycles (after clock divider) that a signal needs to stay below the lower threshold limit before the fd output bits are cleared. filter control (register 0x50) bit 7reserved (reads back as 1) bit 6reserved bit 5reserved (reads back as 1) bit 4fir mode setting this bit low enables the high performance fir filter. setting this bit high enables the low latency fir. bit 3output gain setting this bit high sets the output gain to ?6 db. a 0 value on this bit sets the gain at 0 db.
AD6649 rev. 0 | page 37 of 40 bit 29-bit output mode enable if this bit is set, the ncos and filters are bypassed and the part outputs nine bits of data. these nine bits are presented on the nine msbs of the output bus (that is, bit d13 through bit d5). bits[1:0]datapath gain these bits set the datapath gain as follows: 00 = 0 db gain 01 = ?6 db gain 10 = ?12 db gain 11 = ?18 db gain nco control (register 0x51) bit 7reserved bit 6nco32 to f s /4 nco sync enable this bit should be set high when nco32 is set to f s /4 using the fixed-frequency nco and the 95 mhz fir filter. it should be disabled when using the tunable-frequency nco and 100 mhz fir filter. bit 5spectral reversal this bit should be set high to reverse the output frequency spectrum. bit 4reserved (reads back as 1) bit 3reserved bit 2nco32 amplitude dither enable when bit 2 is set, amplitude dither in the nco is enabled. when bit 2 is cleared, amplitude dither is disabled. bit 1nco32 phase dither enable when bit 2 is set, phase dither in the nco is enabled. when bit 2 is cleared, phase dither is disabled. bit 0reserved (reads back as 1) nco frequency (register 0x52 to register 0x55) register 0x52, bits[7:0]nco frequency value[31:24] register 0x53, bits[7:0]nco frequency value[23:16] register 0x54, bits[7:0]nco frequency value[15:8] register 0x55, bits[7:0]nco frequency value[7:0] this 32-bit value is used to program the nco tuning frequency. the frequency value to be programmed is given by the following equation: clk clk f ffmod nco_freq ),( 2 32 = where: nco_freq is a 32-bit twos complement number representing the nco frequency register. f is the desired carrier frequency in hertz. f clk is the AD6649 adc clock rate in hertz. nco phase offset (register 0x56 and register 0x57) register 0x56, bits[7:0]nco phase value[15:8] register 0x57, bits[7:0]nco phase value[7:0] the 16-bit value programmed into the nco phase value register is loaded into the nco block each time the nco is started or when an nco sync signal is received. this process allows the nco to be started with a known nonzero phase. use the following equation to calculate the nco phase offset value: nco _ phase = 2 16 phase /360 where nco_phase is a decimal number equal to the 16-bit binary number to be programmed at register 0x56 and register 0x57, and phase is the desired nco phase in degrees. sync control (register 0x58) bit 7f s /4 nco next sync only if the master sync buffer enable bit (register 0x3a, bit 0) and the f s /4 nco sync enable bit (register 0x58, bit 6) are high, bit 7 allows the f s /4 nco to synchronize following the first sync pulse that it receives and ignore the rest. if bit 7 is set, bit 6 of register 0x58 resets after this sync occurs. bit 6f s /4 nco sync enable bit 6 gates the sync pulse to the f s /4 nco. when bit 6 is set high, the sync signal causes the f s /4 nco to synchronize. this sync is active only when the master sync buffer enable bit (register 0x3a, bit 0) is high. this is continuous sync mode. bit 5fir next sync only if the master sync buffer enable bit (register 0x3a, bit 0) and the fir sync enable bit (register 0x58, bit 4) are high, bit 5 allows the fir to synchronize following the first sync pulse that it receives and to ignore the rest. if bit 5 is set, bit 4 of register 0x3a resets after this sync occurs. bit 4fir sync enable bit 4 gates the sync pulse to the fir filter. when bit 4 is set high, the sync signal causes the half-band to resynchronize. this sync is active only when the master sync buffer enable bit (register 0x3a, bit 0) is high. this is continuous sync mode. bits[3:2]reserved bit 1nco32 next sync only if the master sync buffer enable bit (register 0x3a, bit 0) and the nco32 sync enable bit (register 0x58, bit 0) are high, bit 1 allows the nco32 to synchronize following the first sync pulse that it receives and to ignore the rest. bit 0 of register 0x58 resets after a sync occurs if bit 1 is set. bit 0nco32 sync enable bit 0 gates the sync pulse to the 32-bit nco. when this bit is set high, the sync signal causes the nco to resynchronize, starting at the nco phase offset value. this sync is active only when the master sync buffer enable bit (register 0x3a, bit 0) is high. this is continuous sync mode.
AD6649 rev. 0 | page 38 of 40 sync pin control (register 0x59) bits[7:2]reserved bit 1sync pin sensitivity if bit 1 is set to a 0, the sync input responds to a level. if this bit is set low, the sync input responds to the edge (rising or falling) set in bit 0 of address 0x59. bit 0sync pin edge sensitivity if bit 1 is set high, setting bit 0 to a 0 causes the sync input to respond to a falling edge. if this bit is set, the sync input respond to a rising edge. nco control 2 (register 0x5a) bits[7:1]reserved bit 0low latency nco select if bit 0 is set to a 1, the low latency nco is selected. this bit should be selected for the fixed-frequency nco, 95 mhz fir filter mode of operation. when this bit is set, the nco value must be set to either 0x40000000 or 0xc0000000.
AD6649 rev. 0 | page 39 of 40 applications information design guidelines before starting system level design and layout of the AD6649, it is recommended that the design er become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. power and ground recommendations when connecting power to the AD6649, it is recommended that two separate 1.8 v supplies be used: one supply should be used for analog (avdd), and a separate supply should be used for the digital outputs (drvdd). the designer can employ several different decoupling capacitors to cover both high and low frequencies. these capacitors should be located close to the point of entry at the pc board level and close to the pins of the part with minimal trace length. a single pcb ground plane should be sufficient when using the AD6649. with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is mandatory that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance. a continuous, exposed (no solder mask) copper plane on the pcb should mate to the AD6649 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be filled or plugged with nonconductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, a silkscreen should be overlaid to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. see the evaluation board for a pcb layout example. for detailed information about packaging and pcb layout of chip scale packages, refer to the an-772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . vcm the vcm pin should be decoupled to ground with a 0.1 f capacitor, as shown in figure 28 . for optimal channel-to-channel isolation, a 33 resistor should be included between the AD6649 vcm pin and the channel a analog input network connection and between the AD6649 vcm pin and the channel b analog input network connection. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6649 to keep these signals from transitioning at the converter inputs during critical sampling periods.
AD6649 rev. 0 | page 40 of 40 outline dimensions compliant to jedec standards mo-220-vmmd-4 091707-c 6.35 6.20 sq 6.05 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) seating plane pin 1 indicator pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 47. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD6649bcpz ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 AD6649bcpzrl7 ?40c to +85c 64-lead lead fr ame chip scale package [lfcsp_vq] cp-64-4 AD6649ebz evaluation board with AD6649 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09635-0-4/11(0)

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